The present invention relates to a semiconductor device comprising circuit blocks with different operation speeds, and further relates to a technology of improving access responsiveness to low-speed circuit blocks in a data processor.
Semiconductor devices such as a system-on-chip data processor having circuit blocks that perform high-speed operation, such as a CPU, and peripheral circuits that perform low-speed serial communication, mounted on the same semiconductor substrate are widely used. In such a kind of semiconductor device, a circuit block that performs high-speed operation is coupled to an on-chip high-speed bus, a circuit block that performs low-speed operation is coupled to an on-chip low-speed bus, and both buses are coupled by a bus bridge circuit. The bus bridge circuit performs timing control on difference of bus access operation in both buses to allow access operation across both buses. Japanese Patent Laid-Open No. 2003-308289, for example, describes a configuration of coupling the low-speed bus and the high-speed bus by a bus bridge circuit.
When the CPU operating at a high speed accesses a peripheral circuit via a low-speed bus, the CPU stalls until a low-speed bus cycle is completed, degrading system performance thereby. Particularly, because operating frequency of peripheral circuits has shown little improvement compared with the recent improvement of operating frequency of the CPU, a large gap has developed between operating frequencies of the low-speed bus and the high-speed bus, making it difficult to bring about a performance that matches the improvement of operating frequency of the CPU.
For example, under the management of a real time OS, interrupt response significantly affects the system performance in an application that frequently uses an interrupt to control built-in devices. In order to respond to an interrupt, the CPU must analyze a cause of the interrupt for an interrupt requestor. In many cases, it is necessary to read a number of internal registers for the peripheral circuit which is the interrupt requestor. In such an occasion, desirable interrupt response cannot be obtained if it takes a long time to access the registers of the peripheral circuit coupling to the low-speed bus.
Although the performance degradation can be avoided by installing a high-speed bus interface in the peripheral circuit operating at a low speed and coupling it to a high-speed bus, employing a high-speed bus interface in many circuits causes undesired increase of power consumption. Since a system-on-chip semiconductor device has many peripheral circuits mounted thereon, this can lead to wasting a large amount of electricity. For example, if more than 20 peripheral circuits are mounted, it is no longer realistic to install a high-speed bus interface in the low-speed peripheral circuit.
The present invention has been made in view of the above circumstances and provides a semiconductor device, and further a data processor, that can improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.
It is another purpose of the present invention to provide a semiconductor device, and further a data processor, that can improve interrupt response without significantly increasing power consumption.
The other purposes and the new feature of the present invention will become clear from the description of the present specification and the accompanying drawings.